As a SoC Implementation Engineer you will work closely with digital and also analog design team to ensure that the deliveries towards Functional Verification / Layout team are provided in time and with the best quality in order to allow reaching the tape-out goals.
In your new role you will :
Work in "Analog on top" and Digital on top flows, implement mixed signal P&R flow and perform LVS, DRC checks on released GDS, implement timing driven and physical constraints.
Generate and handle Clock , reset and LFO trees and perform parasitic extraction .
Implement ECO scripts (timing ECO and functional ECO); perform ECO from code and cells replacement .
Understand synthesis output files (constraints, reports).
Contribute in workshops / COPs / technical meetings / patents / technical conferences and develop / improve / adopt new methodologies for improving current Digital Design flow ( RTL2GDS) .
Provide traceability reports , track and manage found issues .
You demonstrate strong communication skills and know how to establish lasting relationships and networks. You have a team player attitude and a technical drive willing.
Moreover, you are goal and innovation oriented. You actively contribute to putting decisions to work as soon as they are taken and push ideas to their full implementation and application by supporting the team to excellence.
You are best equipped for this task if you have :
A University degree in Electrical / Electronic Engineering or equivalent.
At least 5 years’ experience in SoC implementation .
Proven experience with the following tools : Synopsys / Cadence for P&R , Conformal , Voltage storm , Current density check for analog and digital .
Understanding of Digital Design flow .
Deep knowledge of all steps related to P&R / Digital layout , basic Analog layout knowledge is a plus.
Knowledge of a scripting language (e.g. TCL, bash, Perl, Python).
Good command of English Language .