Your new role challenging and future - oriented We are looking for a Junior R&D engineer for digital IC verification. The required R&D activities cover the whole digital IC verification area, depending on the project needs : specifications, verification planning, definition and implementation of verification environments and components, RTL and reference models implementation, verification and debug at different levels (block, chip, system) using different methodologies, development of automation scripts and results analysis, development of software programs for analysis and system tests, analysis and implementations for new approaches and improvements of the verification and test methodologies.
Your Qualifications Solid and Appropriate BSc / MSc degree in Electrical / Electronics Engineering / Automation / Computer Science 0-3 (junior level) years of experience in digital IC verification and / or design Good understanding of OOP, C / C++ / C# and scripting languages (Perl / Tcl / Python / sh) Good knowledge of digital circuits, hardware description languages (VHDL / Verilog) and / or verification languages (e, SystemVerilog) Knowledge of simulation tools and / or FPGA implementation Good knowledge of computer architectures, data transmission protocols, digital interfaces Nice to have : Experience using verification methodologies (VMM / OVM / UVM / eRM) Knowledge of digital systems modeling (Matlab / Simulink, SystemC) Interpersonal skills needed : team player self-organized aim for a high quality standard willing to learn and discover new things desire for self-improvements and innovations in the area of interest comfortable with processes within a large organization Language skills : English mandatory German is a plus Misc : Occasional or low to medium travelling is required, depending on the project needs Organization : Technology Company : Siemens S.
R.L. Experience Level : Early Professional Job Type : Full-time