EDA TOOL ENGINEER-(2101010)
Influence EDA vendors’ developments on the features, performance and quality of their functional verification tools.
Establish new tools and methodologies increasing the quality of ON Semiconductor’s products.
Continuously make propositions to improve EDA tools environment and methodologies in order to improve designer productivity and satisfaction level.
Support the worldwide design community in using external EDA tools and internally developed scripts and tools.
MS degree or equivalent by experience in Electrical Engineering, Computer Science or related field.
5+ years of functional verification expertise (architect, designer, project lead, etc.).
Experience with functional verification tools (analog, digital & mixed-signal simulation; aging / reliability / ESD / SOA / simulation;
simulation environments; ) from EDA vendors such as Cadence, Mentor, Synopsys
Experience with SystemVerilog & UVM based verification methodology.
Experience with Verilog-A, Verilog-AMS and SystemVerilog behavioral modelling languages.
Experience with Emulation Platforms and Tools.
Experience with Linux as a user environment.
Affinity with programming & scripting languages such as Perl, Bash, TCL, Python, QT, C, C++
Having experience with revision controlled development environments (SVN, Cliosoft, Git).
Excellent analytical and problem-solving skills.
A team player with excellent communication skills verbal and written.
Fluent in English.