Principal Engineer, Physical Design
Bucharest, Romania
4 zile în urmă

About Marvell

At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology.

Trusted by the world’s leading technology companies for 25 years, we move, store, process and secure the world’s data with semiconductor solutions designed for our customers’ current needs and future ambitions.

Through a process of deep collaboration and transparency, we’re ultimately changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform for the better.

The data infrastructure that our customers build has never been more critical to our global economy. It’s what’s keeping the world connected, businesses running, and information flowing.

If you’re ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.

The Opportunity

The proliferation of the data economy is accelerating and creating significant strains on the global data infrastructure.

Built on decades of expertise and execution, Marvell’s custom ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide-array of flexible business models.

Job Responsibilities :

  • As a leading member of Central Physical Design team, you will provide RTL2GDS design service for multiple Marvell SOC design groups, from synthesis, floor planning, power grid design, place and route, clock tree synthesis, timing closure, power / signal integrity signoff to physical verification (DRC / LVS / Antenna).
  • Your role may also include project management and leading a team of physical design engineers on project level.
  • You will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed SOCs, and use your expertise to influence frontend and integration team to ensure successful tapeouts.
  • Your responsibility may include participating in or leading cutting-edge physical design methodology and flow development.
  • Requirements :

  • BS / MS in EE / CS with 10+ years of hands-on experience in CAD back-end physical design and verification. Familiar with hierarchical physical design strategies, methodologies, and deep sub-micron technology issues.
  • Familiar with ASIC design flow, Verilog HDL, synthesis, and timing closure.

  • Proven track records of leading chip level backend implementation activity and taping out complex SOC chips under tight schedule pressure.
  • In-depth understanding of current design technologies used in major foundries.
  • Must be programming-minded, expert on using Makefile / Tcl / Perl / Python to improve efficiency and streamline process.
  • Detail oriented, self-motivated team worker, good verbal and written communication skills.
  • Must be a power user of P&R tools (Innovus, ICC2, Fusion Compiler).
  • Strong knowledge on static timing analysis (PrimeTime, Tempus), EM / IR-Drop / crosstalk analysis (PTSI, Voltus, Redhawk, PrimeRail), extraction (Quantus, StarRC), formal or physical verification (Formality, Verplex, Calibre, Hercules) a plus.
  • The Perks

    With competitive compensation and great benefits, you will enjoy our workstyle within an incredible culture. We’ll give you all the tools you need to succeed so you can grow and develop with us.

    For additional information on what it’s like to work at Marvell, visit our page.

    Your Future

    Marvell provides a work environment that promotes employee growth and development. We are searching for an individual who wants to grow with the company and will strive to improve performance.

    If you are driven, personable, and energetic, there will be additional opportunities for you here at Marvell.

    All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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