To Perform highly optimized Auto Place & Route (APR), chip level layout integration and chip level verification of PIC Microcontrollers to support APR-
related project activities for the MCU16 Division. The products focus in MCU16 division is focused on 16-bit microcontroller design and implementation.
Activities are focused on Physical Design Engineering support as part of a Design Team.
Floor planning and Place and Route at block level and chip level
Custom Clock Tree / Clock Tree Synthesis (CTS) methodology development
Integration of Custom and Digital blocks
Active participation in STA by identifying and executing timing ECO’s
Execute tape out sign off checks (LVS, DRC, EMIR, DFM and Signal-EM)
Interact with the CAD team to ensure coordination on layout related tools / libraries / scripts for cost-effective and timely release
Interface with design engineers to provide feedback and implement enhancements to ensure design correctness and robustness.
BSEE / MSEE in Electronics and Electrical Engineering.
9 to 12 years of experience in Physical design.
Expert user of Synopsys ICC Floor-planning, Place & Route and Clock Tree Synthesis.
Good verbal and written communication skills with local and remote teams.
Experience in Microcontrollers or related physical designs on 90nm / 40nm process node.
Strong debugging skills including STA, CTS and Physical verification.
Experience on RC Extraction, Signal Integrity, IR drop analysis and Crosstalk analysis, good at scripting in TCL, PERL etc.