10137 - Functional Verification Engineer
1 zi în urmă


Language (HDL) VHDL and / or SystemVerilog, Simulation, Regression, Formal Verification (FV), Assertion Base Verification (ABV), Verification IP (VIP).

UNIX / Linux environment Simulation and Verification : Digital simulation (Simulation), Random Pattern Generator, Formal Verification, Property Checks Advantage : VCS, Verdi / DVE


1-3 years of experience

Simulation and Verification : Digital simulation (Simulation)

Random Pattern Generator


  • Private health subscription + hospitalization package
  • Private dental subscription
  • Gym subscription
  • Vouchers / bonuses for special events (birthday, Christmas, Easter, etc)
  • Meal vouchers of 20 RON / working day (legal value)
  • Ability to work with a global company and immerse in a variety of international projects with different cultures within the IT industry
  • Access to cutting edge and state of the art technologies current with the everyday evolvement of technologies
  • Development opportunities with free access to over 3000+ training courses and peer to peer mentoring support
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