10670 - Lead Verification Engineer
Qualitest
Bucharest
1 zi în urmă

Description

Language (HDL) VHDL and / or SystemVerilog

Simulation- Regression- Formal Verification (FV)- Assertion Base Verification (ABV)- Verification IP (VIP)

UNIX / Linux environment

Random Pattern Generator

Property Checks Advantage : VCS- Verdi / DVE

Benefits

  • Private health subscription + hospitalization package
  • Private dental subscription
  • Gym subscription
  • Vouchers / bonuses for special events (birthday, Christmas, Easter, etc)
  • Meal vouchers of 20 RON / working day (legal value)
  • Ability to work with a global company and immerse in a variety of international projects with different cultures within the IT industry
  • Access to cutting edge and state of the art technologies current with the everyday evolvement of technologies
  • Development opportunities with free access to over 3000+ training courses and peer to peer mentoring support
  • Raportați această lucrare
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